R. c. filter with capacitance produced by grain boundary semiconductor



y 1965 w. w. LINDEMANN ETAL 3,196,372

R.C. FILTER WITH CAPACITANCE PRODUCED BY GRAIN BOUNDARY SEMICONDUCTORFiled Jan. 6, 1961 -GRA|N BOUNDARY RESISTIVE LAYER 26 (INTRINSICMATERIAL) ALLOYED CONTACTS E /-22 26 28 m I00 36 3s 252%"? 28 32 23 3228 32 3X'E%ML H 3 DOPED TO GIVE FIG. 2 LOW RESISTANCE INTRINSIC 34 so 226 MATERIAL DOPED 2? 24b MATERIAL 22b 26 I40 3 1 18b m oo so -4, 36 3620b 1 lMATERIAL 30 38/ I2 |6b 32 INTRINSIC l 1 MATERIAL 32 2a 32INTRINSIC 28 IG 6 MATERIAL HQ 5 INVENTORS WALLACE W. LINDEMANN ROLF K.MUELLER BY JM/Z/ZZMW ATTOR N EY United States Patent 3 196,372 RC.FILTER WITH CAPACITANCE PRQDUCED BY GRAIN BQUNDARY SEMICONDUCTGR WallaceW. Lindemann, Minneapolis, and Rolf K. Mueller, St. Paul, Minn,assignors, by mesne assignments, to Littnn Systems, Inc., Beverly Hills,Calif., a curporation of Maryland Filed Jan. 6, 1961, Ser. No. 81,162 9Claims. (Cl. 333-70) This invention relates generally to RC networks andpertains more particularly to networks formed from semiconductive blockshaving a grain boundary incorporated therein.

One important object of the present invention is to provide aminiaturized network that can be easily fabricated. While our inventionwill find utility in various situations, it can be pointed out that itpossesses especial utility in the field of molecular electronics due tothe extremely small size of the networks formed in accordance with theteachings of the instant invention. More specifically, it iscontemplated that networks constructed in accordance with this inventionwill find use as RC filters and delay lines.

Considerable literature, both in periodical form and in the form ofpatents, is currently available with respect to the use of grainboundaries in semiconducting materials. As an example, see the bookDislocations in Crys tals by W. T. Read, Ir. Consequently, it is notbelieved necessary to present the theory surrounding these grainboundaries. However, it may be quite helpful to point out that theresistance values of crystal grain boundaries such as those discussed inthe noted publication can be made very high since they are verytemperature dependent. On the other hand, the capacity values aretemperatures independent at temperatures below room temperature.

Other objects will be in part obvious, and in part pointed out more indetail hereinafter.

The invention accordingly consists in the features of construction,combination of elements and arrangement of parts which will beexemplified in the construction hereafter set forth and the scope of theapplication which will be indicated in the appended claims.

In the drawing:

FIGURE 1 illustrates one embodiment that the invention may assume;

FIG. 2 represents a somewhat modified version of FIG- URE 1, it beingplanned that the embodiment of FIG. 2 will be utilized in substantiallythe same situations as the embodiment of FIGURE 1;

FIG. 3 is a schematic diagram representing the equivalent circuit ofboth FIGURES 1 and 2;

FIG. 4 is a different embodiment from the embodiments pictured inFIGURES 1 and 2;

FIG. 5 is still a different embodiment but possessing the same operatingcharacteristics as the embodiment set forth in FIG. 4, and

FIG. 6 is a schematic diagram representing the equivalent circuit of theembodiments of FIGURES 4 and 5.

Referring first to FIGURE 1, it will be observed that a block ofsemiconductive material labelled 10 has been pictured. One side of theblock 19 has attached thereto a resistive contact 12, and the sideopposite to this particular side has a pair of spaced resistive contacts14, 16 secured thereto. A grain boundary 13 extends from one end of theblock to the other in a generally parallel direction to the sides orfaces to which the contacts 12, 14, and 16 are attached. Through wellknown diffusion techniques, an impurity is introduced into thesemiconductive material to produce a doped region 29 on one side of icethe grain boundary 1% and, similarly, a doped region 22 is provided onthe other side. The semiconductor having the grain boundary is preparedby growing a bicrystal from precisely oriented double seeds. Asemiconductor block is cut from this bicrystal. The doped region 2%} and22 near the grain boundary are produced by uniformly introducing an n orp type impurity into the crystal during the growing process. As moreimpurity is introduced, the doped region becomes larger and leaves lessintrinsic material thus lowering the total resistance (see FIG. 1.) Inthe embodiment now being described, a region of intrinsic or undopedmaterial remains between the region 22 and the contacts 14, 16, thispair of contacts actually being afiixed to the region 24 in the presentinstance. The intrinsic layer is established by making use ofnon-uniform impurity distributions in the bicrystal block. For thepurpose of assisting the reader in orienting himself with respect toboth FIGURES 2 and 3 a terminal 26 has been shown in association withthe contact 14 and a terminal 28 has been shown in association with thecontact 12. These terminals can be considered the input terminals to thenetwork constituting FIGURE 1. On the other hand, a terminal 30 isconnected to the contact 16 and a similar terminal 32 is connected tothe previously mentioned resistive contact 12, the terminals 30, 32serving as output terminals in the illustrative situation. The use ofthese terminals will, however, be better understood when the equivalentcircuit depicted in FIG. 3 is described.

Considering now the embodiment of FIGURE 2, it should be explained atthe outset that this embodiment is quite similar to that of FIGURE 1.Therefore, it will be helpful to utilize the same reference numeralswhere there is a direct similarity, but distinguishing these referencenumerals by the sufiix a. The main difference between the embodiment nowbeing described and the previously referred to embodiment resides in thefact that the alloyed contacts 14:: and 16a are located at opposite endsof the grain boundary 1311, whereas in the previous embodiment thesecontacts were resistive and were located on the intrinsic region 24. Itwill be understood that a grain boundary, such as that with which we arecurrently dealing, has both resistance and capacitance incorporatedthereinto. These resistance and capacitance characteristics areexplained in more complete technical detail in two articles published byRolf K. Mueller. The first, Capacitance and Barrier Height in GrainBoundaries, published April 1959 in volume 30, No. 4, pages 546-550 ofthe Journal of Applied Physics, deals with the capacitancecharacteristics and the second, Captured Diameter of Dislocations in LowAngle Grain Boundaries in Germanium, published in the Journal of Physicsand Chemistry of Solids, Pergamon Press 1959, volume 8, pages 157-161,deals with resistance characteristics. Thus, whereas the intrinsicregion 24 of FIGURE 1 produced the resistance needed in the network, thepresent embodiment utilizes the inherent resistance of the grainboundary itself.

Having described both FIGURES 1 and 2, it will now be of assistance torefer briefly to FIG. 3. In this figure, which is the equivalent circuitof what has been disclosed in FIGURES 1 and 2, the resistance has beendenoted by the reference numeral 34, such resistance extending betweenthe terminals 26 and 30. As indicated immediately above, the resistancecorresponding to that of 34 is provided by the intrinsic region 24 inFIGURE 1 and by the grain boundary itself in FIG. 2. Distributedcapacitance exists between the resistance 34 and the terminals 23, 32.This distributed capacitance has been designated by several capacitors36. In the embodiment of FIGURE 1, the capacitance is provided by thegrain boundary 18, and the grain boundary 13a of PEG. 2 supplies thecapacitance in the second embodiment. in either situation, that is, inusing the embodiment of FIG- URE l or the embodiment of EEG. 2, the cutoff frequency of the network when used as a filter can be varied byapplying a negative bias to the boundary 18 or 13a.

Turning now to the embodiment of FIG. 4, here again certain similaritiesexist and these similarities have been highlighted by utilizing the samereference numerals as with respect to FIGURES 1 and 2, the sufiix bbeing employed as the distinguishing medium. Actually, it will bediscerned that the basic difference between the embodiment now beingreferred to and that of FTGURE 1 re sides in the existence of a secondintrinsic or undoped region labelled 38. In this situation, theresistive contact 12b is attached directly to the layer or region 3%.

With respect to FIG. 5, the suifix c has been utilized.

This embodiment corresponds most closely to that of FIG.

2 and it will be observed that the intrinsic layer or region 380 is thedistinguishing characteristic. This region 38c corresponds, of course,to the region 38 of FIG. 4. ,At any rate,it is readily apparent that theresistive contact 120 of FIG. is attached directly to the region 38c,whereas in FIG. 2 the corresponding contact was affixed to the dopedregion 20a.

While the difference in result is believed manifest from what has beenpresented in the way of explanation with regard to FIGS. 4 and 5,nonetheless attention is called at this time to FIG, 6. As with FIG. 3,FIG. 6 is presented in order to show the equivalent circuitry of FIG-URES 4 and 5. The resistance 34 is the same as that of FIG. 3, and thecapacitance is the same also. 'quently the capacitors appearing in FIG.6 have been given the reference numeral 36. However, it will be notedthat additional resistance in the form of a resistor 40 appears in FIG.6 and not in FIG. 3. The resistance so derived stems from the use of theintrinsic region 33 of FIG. 4 and the similar region Site of FIG. 5. Itwill be recognized that the filter of FIG. 6 is what may succinctly bedescribed as a distributed constant bridged T filter. Here again, thefrequency of the pass band can be adjusted by modifying a bias voltageapplied to the boundary.

RC delay lines can be also readily devised with the configurations thathave been pictured herein.

As many changes could be made in the above construction and manyapparently widely different embodiments of this invention could be madewithout departing from the scope thereof, it is intended that all mattercontained in the description or shown in the accompanying drawings shallbe interpreted as illustrative and not in a limiting sense.

it is also to be understood that the language used in the followingclaims is intended to cover all of the generic and specific features ofthe invention herein described and all statements of the scope of theinvention which, as a matter of language, might be said to falltherebetween.

What is claimed: 1

1. An RC network comprising a block of semiconductive material, a firstcontact at one location on said block and a pair of spaced contacts atdifferent locations on said block, said block including a region ofdoped material provided with contacting crystals having differentspatial orientations, said contacting crystals defining a grain boundarybetween said first contact and said pair of contacts, said region beingbetween said first contact and said pair of contacts.

2. An RC network in accordance with claim 1 in which said block includesa layer of intrinsic material between said pair of contacts and saidgrain boundary.

3. An RC network in accordance with claim 1 in .cluding a region ofintrinsic material between said first contact and said region of dopedmaterial.

Conse 4. An RC network in accordance with claim 1 in which said pair ofcontacts are alioyed and located on said grain boundary.

5. An RC network in accordance with claim 2 in which said pair ofcontacts are resistive and located on said intrinsic material.

6. An RC network in accordance with claim 2 in which said block includesa second region of intrinsic material, said regions of intrinsicmaterial being on opposite sides of said region of doped material withsaid first con tact being resistive and on one of said intrinsic regionsand said pair of contacts being alloyed and on the other of saidintrinsic regions.

'7. An RC filter network comprising a block of semiconductive materialhaving a doped region provided with contacting crystals having differentspatial orientations, said contacting crystals defining a crystal grainboundary having a predetermined capacitance, a layer of intrinsicmaterial contacting said doped region for providing an electricallyresistive region, a pair of terminals connected to said layer in spacedrelationship to provide a predetermined resistance path between theterminals through said layer, and a contact on said block across saidboundary from said terminals for providing a capacitive electrical paththrough said block.

8. An RC network comprising a block of semi-conductive material having adoped region provided with contacting crystals having different spatialorientations, said contacting crystals defining a crystal grain boundaryin said doped region having a predetermined capacitance, a first layerof intrinsic material contacting said doped region at the first side forproviding an electrically resistive region, a second layer of intrinsicmaterial contacting said doped region at a second side for providing anelectrically resistive region, a pair of terminals connected to saidfirst layer in spaced relationship to provide a predetermined resistancepath between said pair of terminals through said first layer, and acontact on said second layer across said boundary from said pair ofterminals for providing a series capacitive and resistive electricalpath through said block.

9. An RC network comprising a block of semiconductive material, a firstresistive contact at one location on said block, and a pair of alloyedcontacts on opposite sides of said block, said block including a regionof doped material spaced from said first resistive contact and providedwith contacting crystals having different spatial orientations, saidcontacting crystals defining a grain boundary extending betwen said pairof alloyed contacts, with said alloyed contacts located on said grainboundary, said blocking including a region of intrinsic -materialbetween said first resistive contact and said region of doped material,said region of intrinsic material being in contact with said firstresistive contact.

References Cited by the Examiner UNITED STATES PATENTS 2,651,831 9/53Bond 317-235 2,889,499 6/59 Rutz 30788.511 2,904,704 9/59 Marinace 30788.541 3,822,472 2/62 Tanenbaum et al 333l8 3,126,505 3/64 Shockley307-88.5 21.4

OTHER REFERENCES Langford, Three Approaches to Microminiaturization,Electronics, Dec. 11, 1959, pages 49-52 relied upon.

Sosnowskh-Electronic Process at Grain Boundaries, Journal Phy.Chem'Solids, vol. 8, pages 142-146, January 1959.

I HERMAN KARL SAALBACH, Primary Examiner.

BENNETT G. MILLER, Examiner.

1. AN RC NETWORK COMPRISING A BLOCK OF SEMICONDUCTIVE MATERIAL, A FIRSTCONTACT AT ONE LOCATION ON SAID BLOCK AND A PAIR OF SPACED CONTACTS ATDIFFERENT LOCATIONS ON SAID BLOCK, SAID BLOCK INCLUDING A REGION OFDOPED MATERIAL PROVIDED WITH CONTACTING CRYSTALS HAVING DIFFERENTSPATIAL ORIENTATIONS, SAID CONTACTING CRYSTALS DEFINING A GRAIN BOUNDARYBETWEEN SAID FIRST CONTACT AND SAID PAIR OF CONTACTS, SAID REGION BEINGBETWEEN SAID FIRST CONTACT AND SAID PAIR OF CONTACTS.